The present disclosure relates generally to nanoscale structures, and more particularly to methods for generating a template pattern for forming a wiring pattern and a cut mask to block regions from forming patterns, and structures for effecting the same.
Unidirectional wiring will likely be used in complementary metal-oxide semiconductor (CMOS) integrated circuit technology beyond the 14 nm node to facilitate the patterning of 1X metal features. Patterning solutions for sub 40 nm pitch wiring are of importance to continue CMOS scaling. While options such as Extreme Ultraviolet (EUV) lithography may possibly be an option, the use of techniques to extend 193 nm immersion (193i) lithography to the sub 40 nm pitch level is of high value.
193i combined with sidewall image transfer 2nd decomposition (SIT2) or self aligned quadruple patterning (SAQP) can produce features below the 40 nm feature pitch. However, overlay for customizing the patterns is beyond the capabilities of conventional lithography tools.
Therefore, methods and structures are needed that extend 193i lithography to sublithographic resolution, with pattern customization achieved either in a self-aligned way or by subsequent customization with relaxed overlay requirements.